An FPGA Implementation of BPNs for FPGA Conf Rev a

An investigation of the implementation and optimization of Beneš Permutation Networks on Field Programmable Gate Arrays (FPGAs) is presented. Specialized design automation tools were used to achieve high performance and efficient area utilization. These tools were used to explore alternative placement and routing strategies, and to take advantage of the underlying FPGA resources. A significant improvement was obtained as compared to standard approaches based on Hardware Description Languages (HDLs) and general synthesis and place and route tools. In addition, several general improvements and extensions were discovered that further improve performance and reduce area.